The present invention generally relates to a method for manufacturing devices that utilize different types of transistors and more particularly to a process that forms all gate oxides in a single step and that simultaneously patterns all gate conductors with different materials in a single step.
Recent advances in integrated circuit chip manufacturing processes have allowed different types of transistors (N-type and P-type) to be simultaneously manufactured on a single chip with the gate conductors for each type formed out of different materials. This allows the integrated circuit chip""s performance to increase without substantially increasing the manufacturing cost or the time needed to manufacture the chips.
However, processes for producing the integrated circuit chips that utilize multiple types of transistors with multiple gate conductor materials can still be streamlined further. For example, many common techniques perform redundant processes to chemically treat previously formed gate conductors differently to create the different types of transistors. However, besides the additional efforts involved in such chemical treatments, they only allow a limited range of possible material modifications without having negative impact on other parts of the device. In addition, some conventional techniques utilize organic film deposition methods; however, such methods often have compatibility problems with post thermal processing. In addition, some conventional processes need to grow the gate oxides separately for the different types of transistors and also need to pattern the different types of gate conductors independently.
The invention described below overcomes these problems and presents a process where the use of organic polymers is avoided, yet where the gate oxide can be formed for all transistors simultaneously and where all gate conductors with different materials for all transistors can be patterned simultaneously. By providing such a methodology, the invention reduces the cost and time needed to manufacture such multiple transistor-type chips, while at the same time increases the yield of the manufacturing process
Described below is a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer (where the gate dielectric could be thin oxide, oxynitride film/stack, or high-k dielectric) depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates in one single step.
The method also planarizes the first-type gate material and the second-type gate material after depositing the second-type gate material. Thus, the first-type gate material and the second-type gate material comprise a continuous layer prior to being patterned into gate conductors. The method also anneals the device after lithographic patterning and pattern transferring processes, wherein the annealing transforms (e.g., joins, combines, etc.) material from the silicon layer into the first-type gate and the second-type gate.
The process of depositing the first-type gate material comprises depositing a silicon germanium layer over the silicon layer and depositing a polysilicon layer over the silicon germanium layer. In another embodiment, a silicon germanium layer deposited with different germanium concentration leads to transistors with different threshold voltages. In other embodiments, the first-type and second-type gate materials can be multi-film stacks, for instance, a film stack with different polycrystalline grain sizes (with smaller grains at the bottom of the gate and larger grains at the top of the gate) for optimum control of gate grain sizes to improve gate depletion at small gate dimensions. In other embodiments, the first-type and second-type gate materials can be metal films and metal silicides, e.g., W and WSix, Ni and NiSix, or Ta and TaSix. The process of depositing the second-type gate material comprises depositing a doped polysilicon material. Unlike conventional dual gate material processes, the silicon layer in this invention protects the gate dielectric layer from yield or reliability losses during the removing of the first-type gate material and the depositing of the second-type gate material, thus reducing costs. The method forms the gate dielectric layer in a single process prior to forming the silicon layer.
The invention provides a process where the gate oxide can be formed for all transistors simultaneously and where all gate conductors with different materials for all transistors can be patterned simultaneously. Unlike conventional dual gate processes that pattern N-type and P-type transistors independently, this process eliminates the alignment problems involved with each resist patterning step which is especially critical at gate level as critical dimension shrinks. This also increases throughput time. By providing such a methodology, the invention reduces the cost and time needed to manufacture such multiple transistor-type chips, while at the same time increases the transistor performance, yield, and reliability of the manufacturing process.
The invention provides a process that offers the flexibility of choosing optimum gate materials for different types of transistors. For instance, N-type transistors benefit from N-type doped (Phosphors or Arsenic) polysilicon gates which give higher electron mobility and better gate activation, while poly SiGe gates improve gate depletion, hole mobility and dopant activation of P-type transistors as well as eliminate boron penetration issues in conventional boron doped poly-Si P-type gates. One can improve gate depletion, carrier mobility, dopant activation and deactivation for different types of transistors and thus improve transistor performance.
In addition, the invention provides a process to offer a tunable work function for N type and P-type transistors independently. For example, by depositing a silicon germanium layer with different germanium concentrations (e.g., 20-50%), devices with different threshold voltages can be embodied in the same chip. Unlike conventional process that uses ion implantation to tailor threshold voltage for different devices, this technique is free from dislocations generated from ion implantation, which in turn lead to increased junction leakage and static power dissipation in circuits.